Processing Time: One major consideration of the proposed design is that of signal processing latency or in speech processing applications, audio latency, the time required between a signal input and the processed signal output. The High-Level programming interface allows for substantial amounts of processing to be conducted at the PC side, with an increase in latency limited by the processing speed of the PC, but primarily to the transfer rates. The Low-Level programming interface allows for the development of processing algorithms that can be executed on a sample-by-sample basis. For example, data sampling rates of 24kHz provide for a 41.667us sampling rate period. This period of time is sufficient to conduct filtering, noise cancellation algorithms and artifact rejection.  Because of the system’s interrupt driven architecture, data can be processed on a sample-by-sample basis while blocks of data can be processed simultaneously. Fast Fourier Transfer (FFT) routines can be implemented on such blocks of data as well as other more advanced processing routines. The signal processing latency can be adjusted by selecting the duration of such buffers as required to accomplish the desired processing functions.

1) Sample-by-Sample DSP Processing:

DSP Interrupt Routines (Clock Dependent)
Acquire -> Process -> Output

The signal processing latency is limited to the sampling period. Data is acquired, processed and the corresponding output generated within the interrupt cycle. Applications include FIR & IIR filtering, ANC and other sample-by sample applications.

2) Sample-by-Sample Preprocessing & Block-Based Higher Level DSP Processing:

DSP Interrupt Routines (Clock Dependent)
Acquire (Buffer(n)) -> Pre-Process -> Output (Buffer(n-2))

Main DSP Rountine (Block Size Dependent)

The signal processing latency is limited to the length of the processing buffer queue. At a rate of 24kHz and using a 256 data point buffers, the latency would be 10.6 msec using this particular dual buffer scheme. The length of the buffer can be adjusted to conform with the latency that is appropriate and acceptable for the specific application.

3) High Level PC Based Processing:

DSP Data Input -> Output Data to PC -> PC Data Processing -> Return Data to DSP -> DSP Data Ouput

The signal processing latency is increased and is limited by the USB transfer rates and PC processing speed. Although these processing latencies might not be optimal for all applications, it provides for a fast initial prototyping requiring less software development and implementation of canned processing routines as those available in TF32, MatLab and other packages.